Synthesis and Ngdbuild Report synthesis: version Diamond (64-bit) 3.13.0.56.2 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved. Sun Feb 11 13:41:47 2024 Command Line: synthesis -f Kurs24_impl1_lattice.synproj -gui -msgset C:/Lattice/Kurs24/promote.xml Synthesis options: The -a option is MachXO2. The -s option is 5. The -t option is TQFP100. The -d option is LCMXO2-1200HC. Using package TQFP100. Using performance grade 5. ########################################################## ### Lattice Family : MachXO2 ### Device : LCMXO2-1200HC ### Package : TQFP100 ### Speed : 5 ########################################################## INFO - synthesis: User-Selected Strategy Settings Optimization goal = Balanced Top-level module name = FrequencyMeter. Target frequency = 200.000000 MHz. Maximum fanout = 1000. Timing path count = 3 BRAM utilization = 100.000000 % DSP usage = true DSP utilization = 100.000000 % fsm_encoding_style = auto resolve_mixed_drivers = 0 fix_gated_clocks = 1 Mux style = Auto Use Carry Chain = true carry_chain_length = 0 Loop Limit = 1950. Use IO Insertion = TRUE Use IO Reg = AUTO Resource Sharing = TRUE Propagate Constants = TRUE Remove Duplicate Registers = TRUE force_gsr = auto ROM style = auto RAM style = auto The -comp option is FALSE. The -syn option is FALSE. -p C:/Lattice/Kurs24 (searchpath added) -p C:/lscc/diamond/3.13/ispfpga/xo2c00/data (searchpath added) -p C:/Lattice/Kurs24/impl1 (searchpath added) -p C:/Lattice/Kurs24 (searchpath added) Verilog design file = C:/Lattice/Kurs24/impl1/source/synchronizer.v Verilog design file = C:/Lattice/Kurs24/impl1/source/edge_detector.v Verilog design file = C:/Lattice/Kurs24/impl1/source/strobe_generator.v Verilog design file = C:/Lattice/Kurs24/impl1/source/double_dabble.v Verilog design file = C:/Lattice/Kurs24/impl1/source/display_multiplex.v Verilog design file = C:/Lattice/Kurs24/impl1/source/decoder_7seg.v Verilog design file = C:/Lattice/Kurs24/impl1/source/frequency_meter.v NGD file = Kurs24_impl1.ngd -sdc option: SDC file input not used. -lpf option: Output file option is ON. Hardtimer checking is enabled (default). The -dt option is not used. The -r option is OFF. [ Remove LOC Properties is OFF. ] Technology check ok... Analyzing Verilog file C:/lscc/diamond/3.13/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 Compile design. Compile Design Begin Analyzing Verilog file c:/lattice/kurs24/impl1/source/synchronizer.v. VERI-1482 Analyzing Verilog file c:/lattice/kurs24/impl1/source/edge_detector.v. VERI-1482 Analyzing Verilog file c:/lattice/kurs24/impl1/source/strobe_generator.v. VERI-1482 Analyzing Verilog file c:/lattice/kurs24/impl1/source/double_dabble.v. VERI-1482 Analyzing Verilog file c:/lattice/kurs24/impl1/source/display_multiplex.v. VERI-1482 Analyzing Verilog file c:/lattice/kurs24/impl1/source/decoder_7seg.v. VERI-1482 Analyzing Verilog file c:/lattice/kurs24/impl1/source/frequency_meter.v. VERI-1482 Analyzing Verilog file C:/lscc/diamond/3.13/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 Top module name (Verilog): FrequencyMeter INFO - synthesis: c:/lattice/kurs24/impl1/source/frequency_meter.v(5): compiling module FrequencyMeter. VERI-1018 INFO - synthesis: c:/lattice/kurs24/impl1/source/synchronizer.v(4): compiling module Synchronizer. VERI-1018 INFO - synthesis: c:/lattice/kurs24/impl1/source/edge_detector.v(4): compiling module EdgeDetector. VERI-1018 INFO - synthesis: c:/lattice/kurs24/impl1/source/strobe_generator.v(4): compiling module StrobeGenerator(CLOCK_HZ=25000000,PERIOD_US=1000000). VERI-1018 INFO - synthesis: c:/lattice/kurs24/impl1/source/double_dabble.v(5): compiling module DoubleDabble(INPUT_BITS=26,OUTPUT_DIGITS=8). VERI-1018 INFO - synthesis: c:/lattice/kurs24/impl1/source/display_multiplex.v(4): compiling module DisplayMultiplex(CLOCK_HZ=25000000). VERI-1018 INFO - synthesis: c:/lattice/kurs24/impl1/source/strobe_generator.v(4): compiling module StrobeGenerator(CLOCK_HZ=25000000,PERIOD_US=1000). VERI-1018 INFO - synthesis: c:/lattice/kurs24/impl1/source/decoder_7seg.v(4): compiling module Decoder7seg. VERI-1018 Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/or5g00/data/orc5glib.ngl'... Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.13/ispfpga. Package Status: Final Version 1.44. Top-level module name = FrequencyMeter. GSR instance connected to net Reset_c. Applying 200.000000 MHz constraint to all clocks WARNING - synthesis: No user .sdc file. Results of NGD DRC are available in FrequencyMeter_drc.log. Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/or5g00/data/orc5glib.ngl'... All blocks are expanded and NGD expansion is successful. Writing NGD file Kurs24_impl1.ngd. ################### Begin Area Report (FrequencyMeter)###################### Number of register bits => 173 of 1520 (11 % ) CCU2D => 35 FD1P3AX => 63 FD1P3IX => 61 FD1S3AX => 8 FD1S3IX => 16 FD1S3JX => 25 GSR => 1 IB => 3 L6MUX21 => 4 LUT4 => 167 OB => 16 PFUMX => 9 ################### End Area Report ################## ################### Begin BlackBox Report ###################### TSALL => 1 ################### End BlackBox Report ################## ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 1 Net : Clock_c, loads : 173 Clock Enable Nets Number of Clock Enables: 7 Top 7 highest fanout Clock Enables: Net : DoubleDabble_inst/Clock_c_enable_121, loads : 32 Net : DoubleDabble_inst/Clock_c_enable_88, loads : 26 Net : Clock_c_enable_90, loads : 26 Net : DoubleDabble_inst/Clock_c_enable_61, loads : 3 Net : DoubleDabble_inst/Clock_c_enable_63, loads : 2 Net : Clock_c_enable_57, loads : 1 Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : StrobeGenerator_inst/n1713, loads : 49 Net : DoubleDabble_inst/State, loads : 39 Net : StrobeGenerator_inst/n1712, loads : 34 Net : Clock_c_enable_57, loads : 32 Net : DoubleDabble_inst/Clock_c_enable_121, loads : 32 Net : DisplayMultiplex_inst/TempData_3_N_333_2, loads : 30 Net : StrobeGenerator_inst/Strobe_o_N_116, loads : 28 Net : Clock_c_enable_90, loads : 26 Net : DoubleDabble_inst/Clock_c_enable_88, loads : 26 Net : DisplayMultiplex_inst/TempData_3_N_333_3, loads : 20 ################### End Clock Report ################## Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 5.000000 -name | | | clk0 [get_nets Clock_c] | 200.000 MHz| 139.237 MHz| 5 * | | | -------------------------------------------------------------------------------- 1 constraints not met. Peak Memory Usage: 58.441 MB -------------------------------------------------------------- Elapsed CPU time for LSE flow : 0.422 secs --------------------------------------------------------------