Lattice Mapping Report File for Design Module 'FrequencyMeter'



Design Information

Command line:   map -a MachXO2 -p LCMXO2-1200HC -t TQFP100 -s 5 -oc Commercial
     Kurs24_impl1.ngd -o Kurs24_impl1_map.ncd -pr Kurs24_impl1.prf -mp
     Kurs24_impl1.mrp -lpf C:/Lattice/Kurs24/impl1/Kurs24_impl1.lpf -lpf
     C:/Lattice/Kurs24/Kurs24.lpf -c 0 -gui 
Target Vendor:  LATTICE
Target Device:  LCMXO2-1200HCTQFP100
Target Performance:   5
Mapper:  xo2c00,  version:  Diamond (64-bit) 3.13.0.56.2
Mapped on:  02/08/24  21:41:53


Design Summary
   Number of registers:    173 out of  1520 (11%)
      PFU registers:          173 out of  1280 (14%)
      PIO registers:            0 out of   240 (0%)
   Number of SLICEs:       119 out of   640 (19%)
      SLICEs as Logic/ROM:    119 out of   640 (19%)
      SLICEs as RAM:            0 out of   480 (0%)
      SLICEs as Carry:         35 out of   640 (5%)
   Number of LUT4s:        238 out of  1280 (19%)
      Number used as logic LUTs:        168
      Number used as distributed RAM:     0
      Number used as ripple logic:       70
      Number used as shift registers:     0
   Number of PIO sites used: 19 + 4(JTAG) out of 80 (29%)
   Number of block RAMs:  0 out of 7 (0%)
   Number of GSRs:        1 out of 1 (100%)
   EFB used :        No
   JTAG used :       No
   Readback used :   No
   Oscillator used : No
   Startup used :    No
   POR :             On
   Bandgap :         On
   Number of Power Controller:  0 out of 1 (0%)
   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
   Number of Dynamic Bank Controller (BCLVDSO):  0 out of 1 (0%)
   Number of DCCA:  0 out of 8 (0%)
   Number of DCMA:  0 out of 2 (0%)
   Number of PLLs:  0 out of 1 (0%)
   Number of DQSDLLs:  0 out of 2 (0%)
   Number of CLKDIVC:  0 out of 4 (0%)
   Number of ECLKSYNCA:  0 out of 4 (0%)
   Number of ECLKBRIDGECS:  0 out of 2 (0%)
   Notes:-
      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
     distributed RAMs) + 2*(Number of ripple logic)
      2. Number of logic LUT4s does not include count of distributed RAM and
     ripple logic.
   Number of clocks:  1
     Net Clock_c: 97 loads, 97 rising, 0 falling (Driver: PIO Clock )
   Number of Clock Enables:  7
     Net Clock_c_enable_57: 17 loads, 17 LSLICEs
     Net DoubleDabble_inst/Clock_c_enable_61: 3 loads, 3 LSLICEs

     Net DoubleDabble_inst/Clock_c_enable_88: 14 loads, 14 LSLICEs
     Net DoubleDabble_inst/Clock_c_enable_63: 2 loads, 2 LSLICEs
     Net DoubleDabble_inst/Clock_c_enable_121: 16 loads, 16 LSLICEs
     Net Clock_c_enable_90: 15 loads, 15 LSLICEs
     Net DisplayMultiplex_inst/SwitchCathode_o: 2 loads, 2 LSLICEs
   Number of LSRs:  5
     Net StrobeGenerator_inst/Strobe_o_N_116: 13 loads, 13 LSLICEs
     Net OneSecondStrobe: 7 loads, 7 LSLICEs
     Net n1713: 28 loads, 28 LSLICEs
     Net DoubleDabble_inst/n971: 1 loads, 1 LSLICEs
     Net DisplayMultiplex_inst/StrobeGenerator0/Strobe_o_N_375: 8 loads, 8
     LSLICEs
   Number of nets driven by tri-state buffers:  0
   Top 10 highest fanout non-clock nets:
     Net DoubleDabble_inst/State: 39 loads
     Net n1712: 35 loads
     Net DisplayMultiplex_inst/TempData_3_N_333_2: 30 loads
     Net n1713: 28 loads
     Net DisplayMultiplex_inst/TempData_3_N_333_3: 20 loads
     Net Clock_c_enable_57: 17 loads
     Net DoubleDabble_inst/Clock_c_enable_121: 16 loads
     Net StrobeGenerator_inst/Strobe_o_N_116: 16 loads
     Net Clock_c_enable_90: 15 loads
     Net DoubleDabble_inst/Clock_c_enable_88: 14 loads




   Number of warnings:  0
   Number of errors:    0
     




Design Errors/Warnings

   No errors or warnings present.



IO (PIO) Attributes

+---------------------+-----------+-----------+------------+
| IO Name             | Direction | Levelmode | IO         |
|                     |           |  IO_TYPE  | Register   |
+---------------------+-----------+-----------+------------+
| Cathodes_o[3]       | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| Cathodes_o[6]       | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| Cathodes_o[7]       | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| Cathodes_o[4]       | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| Cathodes_o[5]       | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| SignalAsync_i       | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+

| Reset               | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| Clock               | INPUT     | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| Segments_o[0]       | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| Segments_o[1]       | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| Segments_o[2]       | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| Segments_o[3]       | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| Segments_o[4]       | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| Segments_o[5]       | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| Segments_o[6]       | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| Segments_o[7]       | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| Cathodes_o[0]       | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| Cathodes_o[1]       | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+
| Cathodes_o[2]       | OUTPUT    | LVCMOS33  |            |
+---------------------+-----------+-----------+------------+



Removed logic

Block i1306 undriven or does not drive anything - clipped.
Signal VCC_net undriven or does not drive anything - clipped.
Signal DisplayMultiplex_inst/StrobeGenerator0/sub_6_add_2_1/S0 undriven or does
     not drive anything - clipped.
Signal DisplayMultiplex_inst/StrobeGenerator0/sub_6_add_2_1/CI undriven or does
     not drive anything - clipped.
Signal DisplayMultiplex_inst/StrobeGenerator0/sub_6_add_2_15/CO undriven or does
     not drive anything - clipped.
Signal add_5_1/S0 undriven or does not drive anything - clipped.
Signal add_5_1/CI undriven or does not drive anything - clipped.
Signal add_5_27/S1 undriven or does not drive anything - clipped.
Signal add_5_27/CO undriven or does not drive anything - clipped.
Signal StrobeGenerator_inst/sub_6_add_2_1/S0 undriven or does not drive anything
     - clipped.
Signal StrobeGenerator_inst/sub_6_add_2_1/CI undriven or does not drive anything
     - clipped.
Signal StrobeGenerator_inst/sub_6_add_2_25/CO undriven or does not drive
     anything - clipped.

     



GSR Usage
---------

GSR Component:
   The Global Set Reset (GSR) resource has been used to implement a global reset

        of the design. The reset signal used for GSR control is 'Reset_c'.
        

     GSR Property:
   The design components with GSR property set to ENABLED will respond to global
        set reset while the components with GSR property set to DISABLED will
        not.
        

     Components with synchronous local reset also reset by asynchronous GSR
----------------------------------------------------------------------

     These components have the GSR property set to ENABLED and the local reset
     is synchronous. The components will respond to the synchronous local reset
     and to the unrelated asynchronous reset signal 'Reset_c' via the GSR
     component.

     Type and number of components of the type: 
   Register = 102 

     Type and instance name of component: 
   Register : StrobeGenerator_inst/Counter_i0
   Register : StrobeGenerator_inst/Counter_i8
   Register : StrobeGenerator_inst/Counter_i7
   Register : StrobeGenerator_inst/Counter_i6
   Register : StrobeGenerator_inst/Counter_i5
   Register : StrobeGenerator_inst/Counter_i4
   Register : StrobeGenerator_inst/Counter_i3
   Register : StrobeGenerator_inst/Counter_i2
   Register : StrobeGenerator_inst/Counter_i1
   Register : StrobeGenerator_inst/Counter_i24
   Register : StrobeGenerator_inst/Counter_i23
   Register : StrobeGenerator_inst/Counter_i22
   Register : StrobeGenerator_inst/Counter_i21
   Register : StrobeGenerator_inst/Counter_i20
   Register : StrobeGenerator_inst/Counter_i19
   Register : StrobeGenerator_inst/Counter_i18
   Register : StrobeGenerator_inst/Counter_i17
   Register : StrobeGenerator_inst/Counter_i16
   Register : StrobeGenerator_inst/Counter_i15
   Register : StrobeGenerator_inst/Counter_i14
   Register : StrobeGenerator_inst/Counter_i13
   Register : StrobeGenerator_inst/Counter_i12
   Register : StrobeGenerator_inst/Counter_i11
   Register : StrobeGenerator_inst/Counter_i10
   Register : StrobeGenerator_inst/Counter_i9
   Register : DoubleDabble_inst/BCD__i0
   Register : DoubleDabble_inst/State_95
   Register : DoubleDabble_inst/BCD__i31
   Register : DoubleDabble_inst/BCD__i30
   Register : DoubleDabble_inst/BCD__i29
   Register : DoubleDabble_inst/BCD__i28
   Register : DoubleDabble_inst/BCD__i27
   Register : DoubleDabble_inst/BCD__i26
   Register : DoubleDabble_inst/BCD__i25
   Register : DoubleDabble_inst/BCD__i24

   Register : DoubleDabble_inst/BCD__i23
   Register : DoubleDabble_inst/BCD__i22
   Register : DoubleDabble_inst/BCD__i21
   Register : DoubleDabble_inst/BCD__i20
   Register : DoubleDabble_inst/BCD__i19
   Register : DoubleDabble_inst/BCD__i18
   Register : DoubleDabble_inst/BCD__i17
   Register : DoubleDabble_inst/BCD__i16
   Register : DoubleDabble_inst/BCD__i15
   Register : DoubleDabble_inst/BCD__i14
   Register : DoubleDabble_inst/BCD__i13
   Register : DoubleDabble_inst/BCD__i12
   Register : DoubleDabble_inst/BCD__i11
   Register : DoubleDabble_inst/BCD__i10
   Register : DoubleDabble_inst/BCD__i9
   Register : DoubleDabble_inst/BCD__i8
   Register : DoubleDabble_inst/BCD__i7
   Register : DoubleDabble_inst/BCD__i6
   Register : DoubleDabble_inst/BCD__i5
   Register : DoubleDabble_inst/BCD__i4
   Register : DoubleDabble_inst/BCD__i3
   Register : DoubleDabble_inst/BCD__i2
   Register : DoubleDabble_inst/BCD__i1
   Register : DoubleDabble_inst/Binary_i0
   Register : DoubleDabble_inst/Counter_i2
   Register : DoubleDabble_inst/Counter_i1
   Register : Counter__i20
   Register : Counter__i19
   Register : Counter__i18
   Register : Counter__i17
   Register : Counter__i1
   Register : Counter__i16
   Register : Counter__i15
   Register : Counter__i0
   Register : Counter__i2
   Register : Counter__i4
   Register : Counter__i25
   Register : Counter__i14
   Register : Counter__i13
   Register : Counter__i24
   Register : Counter__i23
   Register : Counter__i12
   Register : Counter__i11
   Register : Counter__i22
   Register : Counter__i3
   Register : Counter__i10
   Register : Counter__i9
   Register : Counter__i8
   Register : Counter__i7
   Register : Counter__i6
   Register : Counter__i21
   Register : Counter__i5
   Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i0
   Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i1
   Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i2
   Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i3

   Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i4
   Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i5
   Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i6
   Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i7
   Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i8
   Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i9
   Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i10
   Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i11
   Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i12
   Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i13
   Register : DisplayMultiplex_inst/StrobeGenerator0/Counter_i14



Run Time and Memory Usage
-------------------------

   Total CPU Time: 0 secs  
   Total REAL Time: 0 secs  
   Peak Memory Usage: 41 MB
        








































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