Lattice Synthesis Timing Report
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Lattice Synthesis Timing Report, Version  
Sun Feb 11 13:41:48 2024

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2023 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Design:     FrequencyMeter
Constraint file:  
Report level:    verbose report, limited to 3 items per constraint
--------------------------------------------------------------------------------



================================================================================
Constraint: create_clock -period 5.000000 -name clk0 [get_nets Clock_c]
            1137 items scored, 649 timing errors detected.
--------------------------------------------------------------------------------


Error:  The following path violates requirements by 2.182ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1P3IX    CK             \DoubleDabble_inst/Counter_i1  (from Clock_c +)
   Destination:    FD1P3AX    D              \DoubleDabble_inst/Counter_i4  (to Clock_c +)

   Delay:                   7.036ns  (31.2% logic, 68.8% route), 5 logic levels.

 Constraint Details:

      7.036ns data_path \DoubleDabble_inst/Counter_i1 to \DoubleDabble_inst/Counter_i4 violates
      5.000ns delay constraint less
      0.146ns L_S requirement (totaling 4.854ns) by 2.182ns

 Path Details: \DoubleDabble_inst/Counter_i1 to \DoubleDabble_inst/Counter_i4

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.403             CK to Q              \DoubleDabble_inst/Counter_i1 (from Clock_c)
Route         5   e 1.222                                  \DoubleDabble_inst/Counter[1]_adj_385
LUT4        ---     0.448              A to Z              \DoubleDabble_inst/i1_2_lut
Route         1   e 0.788                                  \DoubleDabble_inst/n6
LUT4        ---     0.448              D to Z              \DoubleDabble_inst/i4_4_lut_rep_26
Route         7   e 1.255                                  \DoubleDabble_inst/n1631
LUT4        ---     0.448              B to Z              \DoubleDabble_inst/i434_2_lut_rep_16_3_lut_4_lut
Route         1   e 0.788                                  \DoubleDabble_inst/n1621
LUT4        ---     0.448              D to Z              \DoubleDabble_inst/i795_4_lut
Route         1   e 0.788                                  \DoubleDabble_inst/Counter_4__N_209[4]
                  --------
                    7.036  (31.2% logic, 68.8% route), 5 logic levels.


Error:  The following path violates requirements by 2.182ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1P3IX    CK             \DoubleDabble_inst/Counter_i1  (from Clock_c +)
   Destination:    FD1P3AX    D              \DoubleDabble_inst/Counter_i3  (to Clock_c +)

   Delay:                   7.036ns  (31.2% logic, 68.8% route), 5 logic levels.

 Constraint Details:

      7.036ns data_path \DoubleDabble_inst/Counter_i1 to \DoubleDabble_inst/Counter_i3 violates
      5.000ns delay constraint less
      0.146ns L_S requirement (totaling 4.854ns) by 2.182ns

 Path Details: \DoubleDabble_inst/Counter_i1 to \DoubleDabble_inst/Counter_i3

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.403             CK to Q              \DoubleDabble_inst/Counter_i1 (from Clock_c)
Route         5   e 1.222                                  \DoubleDabble_inst/Counter[1]_adj_385
LUT4        ---     0.448              A to Z              \DoubleDabble_inst/i1_2_lut
Route         1   e 0.788                                  \DoubleDabble_inst/n6
LUT4        ---     0.448              D to Z              \DoubleDabble_inst/i4_4_lut_rep_26
Route         7   e 1.255                                  \DoubleDabble_inst/n1631
LUT4        ---     0.448              B to Z              \DoubleDabble_inst/i427_2_lut_rep_17_3_lut
Route         1   e 0.788                                  \DoubleDabble_inst/n1622
LUT4        ---     0.448              B to Z              \DoubleDabble_inst/i796_3_lut_4_lut
Route         1   e 0.788                                  \DoubleDabble_inst/Counter_4__N_209[3]
                  --------
                    7.036  (31.2% logic, 68.8% route), 5 logic levels.


Error:  The following path violates requirements by 1.974ns

 Logical Details:  Cell type  Pin type       Cell name  (clock net +/-)

   Source:         FD1P3IX    CK             \DoubleDabble_inst/Counter_i1  (from Clock_c +)
   Destination:    FD1P3AX    SP             \DoubleDabble_inst/BCD_o_i0_i0  (to Clock_c +)

   Delay:                   6.715ns  (26.0% logic, 74.0% route), 4 logic levels.

 Constraint Details:

      6.715ns data_path \DoubleDabble_inst/Counter_i1 to \DoubleDabble_inst/BCD_o_i0_i0 violates
      5.000ns delay constraint less
      0.259ns LCE_S requirement (totaling 4.741ns) by 1.974ns

 Path Details: \DoubleDabble_inst/Counter_i1 to \DoubleDabble_inst/BCD_o_i0_i0

   Name    Fanout   Delay (ns)          Pins               Resource(Cell.Net)
L_CO        ---     0.403             CK to Q              \DoubleDabble_inst/Counter_i1 (from Clock_c)
Route         5   e 1.222                                  \DoubleDabble_inst/Counter[1]_adj_385
LUT4        ---     0.448              A to Z              \DoubleDabble_inst/i1_2_lut
Route         1   e 0.788                                  \DoubleDabble_inst/n6
LUT4        ---     0.448              D to Z              \DoubleDabble_inst/i4_4_lut_rep_26
Route         7   e 1.255                                  \DoubleDabble_inst/n1631
LUT4        ---     0.448              C to Z              \DoubleDabble_inst/i1230_3_lut_4_lut
Route        32   e 1.703                                  \DoubleDabble_inst/Clock_c_enable_121
                  --------
                    6.715  (26.0% logic, 74.0% route), 4 logic levels.

Warning: 7.182 ns is the maximum delay for this constraint.


Timing Report Summary
--------------
--------------------------------------------------------------------------------
Constraint                              |   Constraint|       Actual|Levels
--------------------------------------------------------------------------------
                                        |             |             |
create_clock -period 5.000000 -name     |             |             |
clk0 [get_nets Clock_c]                 |     5.000 ns|     7.182 ns|     5 *
                                        |             |             |
--------------------------------------------------------------------------------


1 constraints not met.

--------------------------------------------------------------------------------
Critical Nets                           |   Loads|  Errors| % of total
--------------------------------------------------------------------------------
\StrobeGenerator_inst/Strobe_o_N_116    |      28|     364|     56.09%
                                        |        |        |
\StrobeGenerator_inst/n1522             |       1|     196|     30.20%
                                        |        |        |
\DoubleDabble_inst/n1631                |       7|     178|     27.43%
                                        |        |        |
\StrobeGenerator_inst/n46               |       1|     168|     25.89%
                                        |        |        |
\DoubleDabble_inst/Clock_c_enable_121   |      32|     160|     24.65%
                                        |        |        |
\StrobeGenerator_inst/n42               |       1|     112|     17.26%
                                        |        |        |
\StrobeGenerator_inst/n43               |       1|     112|     17.26%
                                        |        |        |
\StrobeGenerator_inst/n38               |       1|      84|     12.94%
                                        |        |        |
\DoubleDabble_inst/n6                   |       1|      76|     11.71%
                                        |        |        |
--------------------------------------------------------------------------------


Timing summary:
---------------

Timing errors: 649  Score: 704203

Constraints cover  2700 paths, 356 nets, and 1067 connections (83.0% coverage)


Peak memory: 61210624 bytes, TRCE: 2027520 bytes, DLYMAN: 167936 bytes
CPU_TIME_REPORT: 0 secs