Place & Route TRACE Report

Loading design for application trce from file kurs24_impl1.ncd.
Design name: FrequencyMeter
NCD version: 3.3
Vendor:      LATTICE
Device:      LCMXO2-1200HC
Package:     TQFP100
Performance: 5
Loading device for application trce from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.13/ispfpga.
Package Status:                     Final          Version 1.44.
Performance Hardware Data Status:   Final          Version 34.4.
Setup and Hold Report

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Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.13.0.56.2
Thu Feb 08 21:41:58 2024

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2023 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
------------------
Command line:    trce -v 10 -gt -sethld -sp 5 -sphld m -o Kurs24_impl1.twr -gui Kurs24_impl1.ncd Kurs24_impl1.prf 
Design file:     kurs24_impl1.ncd
Preference file: kurs24_impl1.prf
Device,speed:    LCMXO2-1200HC,5
Report level:    verbose report, limited to 10 items per preference
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Preference Summary

  • FREQUENCY NET "Clock_c" 25.000000 MHz (0 errors)
  • 2010 items scored, 0 timing errors detected. Report: 126.791MHz is the maximum frequency for this preference. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "Clock_c" 25.000000 MHz ; 2010 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 32.113ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q StrobeGenerator_inst/Counter_i21 (from Clock_c +) Destination: FF Data in StrobeGenerator_inst/Counter_i20 (to Clock_c +) FF StrobeGenerator_inst/Counter_i19 Delay: 7.639ns (23.1% logic, 76.9% route), 4 logic levels. Constraint Details: 7.639ns physical path delay StrobeGenerator_inst/SLICE_1 to StrobeGenerator_inst/SLICE_2 meets 40.000ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 39.752ns) by 32.113ns Physical Path Details: Data path StrobeGenerator_inst/SLICE_1 to StrobeGenerator_inst/SLICE_2: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R10C13D.CLK to R10C13D.Q0 StrobeGenerator_inst/SLICE_1 (from Clock_c) ROUTE 2 1.331 R10C13D.Q0 to R7C14A.A0 StrobeGenerator_inst/Counter_21 CTOF_DEL --- 0.452 R7C14A.A0 to R7C14A.F0 SLICE_97 ROUTE 1 1.057 R7C14A.F0 to R10C14C.C1 StrobeGenerator_inst/n32 CTOF_DEL --- 0.452 R10C14C.C1 to R10C14C.F1 SLICE_108 ROUTE 1 1.324 R10C14C.F1 to R7C12C.A0 StrobeGenerator_inst/n46 CTOF_DEL --- 0.452 R7C12C.A0 to R7C12C.F0 StrobeGenerator_inst/SLICE_93 ROUTE 16 2.162 R7C12C.F0 to R10C13C.LSR StrobeGenerator_inst/Strobe_o_N_116 (to Clock_c) -------- 7.639 (23.1% logic, 76.9% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to StrobeGenerator_inst/SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 97 2.001 20.PADDI to R10C13D.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to StrobeGenerator_inst/SLICE_2: Name Fanout Delay (ns) Site Resource ROUTE 97 2.001 20.PADDI to R10C13C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 32.113ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q StrobeGenerator_inst/Counter_i21 (from Clock_c +) Destination: FF Data in StrobeGenerator_inst/Counter_i8 (to Clock_c +) FF StrobeGenerator_inst/Counter_i7 Delay: 7.639ns (23.1% logic, 76.9% route), 4 logic levels. Constraint Details: 7.639ns physical path delay StrobeGenerator_inst/SLICE_1 to StrobeGenerator_inst/SLICE_8 meets 40.000ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 39.752ns) by 32.113ns Physical Path Details: Data path StrobeGenerator_inst/SLICE_1 to StrobeGenerator_inst/SLICE_8: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R10C13D.CLK to R10C13D.Q0 StrobeGenerator_inst/SLICE_1 (from Clock_c) ROUTE 2 1.331 R10C13D.Q0 to R7C14A.A0 StrobeGenerator_inst/Counter_21 CTOF_DEL --- 0.452 R7C14A.A0 to R7C14A.F0 SLICE_97 ROUTE 1 1.057 R7C14A.F0 to R10C14C.C1 StrobeGenerator_inst/n32 CTOF_DEL --- 0.452 R10C14C.C1 to R10C14C.F1 SLICE_108 ROUTE 1 1.324 R10C14C.F1 to R7C12C.A0 StrobeGenerator_inst/n46 CTOF_DEL --- 0.452 R7C12C.A0 to R7C12C.F0 StrobeGenerator_inst/SLICE_93 ROUTE 16 2.162 R7C12C.F0 to R10C12A.LSR StrobeGenerator_inst/Strobe_o_N_116 (to Clock_c) -------- 7.639 (23.1% logic, 76.9% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to StrobeGenerator_inst/SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 97 2.001 20.PADDI to R10C13D.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to StrobeGenerator_inst/SLICE_8: Name Fanout Delay (ns) Site Resource ROUTE 97 2.001 20.PADDI to R10C12A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 32.113ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q StrobeGenerator_inst/Counter_i21 (from Clock_c +) Destination: FF Data in StrobeGenerator_inst/Counter_i4 (to Clock_c +) FF StrobeGenerator_inst/Counter_i3 Delay: 7.639ns (23.1% logic, 76.9% route), 4 logic levels. Constraint Details: 7.639ns physical path delay StrobeGenerator_inst/SLICE_1 to StrobeGenerator_inst/SLICE_10 meets 40.000ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 39.752ns) by 32.113ns Physical Path Details: Data path StrobeGenerator_inst/SLICE_1 to StrobeGenerator_inst/SLICE_10: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R10C13D.CLK to R10C13D.Q0 StrobeGenerator_inst/SLICE_1 (from Clock_c) ROUTE 2 1.331 R10C13D.Q0 to R7C14A.A0 StrobeGenerator_inst/Counter_21 CTOF_DEL --- 0.452 R7C14A.A0 to R7C14A.F0 SLICE_97 ROUTE 1 1.057 R7C14A.F0 to R10C14C.C1 StrobeGenerator_inst/n32 CTOF_DEL --- 0.452 R10C14C.C1 to R10C14C.F1 SLICE_108 ROUTE 1 1.324 R10C14C.F1 to R7C12C.A0 StrobeGenerator_inst/n46 CTOF_DEL --- 0.452 R7C12C.A0 to R7C12C.F0 StrobeGenerator_inst/SLICE_93 ROUTE 16 2.162 R7C12C.F0 to R10C11C.LSR StrobeGenerator_inst/Strobe_o_N_116 (to Clock_c) -------- 7.639 (23.1% logic, 76.9% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to StrobeGenerator_inst/SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 97 2.001 20.PADDI to R10C13D.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to StrobeGenerator_inst/SLICE_10: Name Fanout Delay (ns) Site Resource ROUTE 97 2.001 20.PADDI to R10C11C.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 32.113ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q StrobeGenerator_inst/Counter_i21 (from Clock_c +) Destination: FF Data in StrobeGenerator_inst/Counter_i6 (to Clock_c +) FF StrobeGenerator_inst/Counter_i5 Delay: 7.639ns (23.1% logic, 76.9% route), 4 logic levels. Constraint Details: 7.639ns physical path delay StrobeGenerator_inst/SLICE_1 to StrobeGenerator_inst/SLICE_9 meets 40.000ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 39.752ns) by 32.113ns Physical Path Details: Data path StrobeGenerator_inst/SLICE_1 to StrobeGenerator_inst/SLICE_9: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R10C13D.CLK to R10C13D.Q0 StrobeGenerator_inst/SLICE_1 (from Clock_c) ROUTE 2 1.331 R10C13D.Q0 to R7C14A.A0 StrobeGenerator_inst/Counter_21 CTOF_DEL --- 0.452 R7C14A.A0 to R7C14A.F0 SLICE_97 ROUTE 1 1.057 R7C14A.F0 to R10C14C.C1 StrobeGenerator_inst/n32 CTOF_DEL --- 0.452 R10C14C.C1 to R10C14C.F1 SLICE_108 ROUTE 1 1.324 R10C14C.F1 to R7C12C.A0 StrobeGenerator_inst/n46 CTOF_DEL --- 0.452 R7C12C.A0 to R7C12C.F0 StrobeGenerator_inst/SLICE_93 ROUTE 16 2.162 R7C12C.F0 to R10C11D.LSR StrobeGenerator_inst/Strobe_o_N_116 (to Clock_c) -------- 7.639 (23.1% logic, 76.9% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to StrobeGenerator_inst/SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 97 2.001 20.PADDI to R10C13D.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to StrobeGenerator_inst/SLICE_9: Name Fanout Delay (ns) Site Resource ROUTE 97 2.001 20.PADDI to R10C11D.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 32.113ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q StrobeGenerator_inst/Counter_i21 (from Clock_c +) Destination: FF Data in StrobeGenerator_inst/Counter_i2 (to Clock_c +) FF StrobeGenerator_inst/Counter_i1 Delay: 7.639ns (23.1% logic, 76.9% route), 4 logic levels. Constraint Details: 7.639ns physical path delay StrobeGenerator_inst/SLICE_1 to StrobeGenerator_inst/SLICE_11 meets 40.000ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 39.752ns) by 32.113ns Physical Path Details: Data path StrobeGenerator_inst/SLICE_1 to StrobeGenerator_inst/SLICE_11: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R10C13D.CLK to R10C13D.Q0 StrobeGenerator_inst/SLICE_1 (from Clock_c) ROUTE 2 1.331 R10C13D.Q0 to R7C14A.A0 StrobeGenerator_inst/Counter_21 CTOF_DEL --- 0.452 R7C14A.A0 to R7C14A.F0 SLICE_97 ROUTE 1 1.057 R7C14A.F0 to R10C14C.C1 StrobeGenerator_inst/n32 CTOF_DEL --- 0.452 R10C14C.C1 to R10C14C.F1 SLICE_108 ROUTE 1 1.324 R10C14C.F1 to R7C12C.A0 StrobeGenerator_inst/n46 CTOF_DEL --- 0.452 R7C12C.A0 to R7C12C.F0 StrobeGenerator_inst/SLICE_93 ROUTE 16 2.162 R7C12C.F0 to R10C11B.LSR StrobeGenerator_inst/Strobe_o_N_116 (to Clock_c) -------- 7.639 (23.1% logic, 76.9% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to StrobeGenerator_inst/SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 97 2.001 20.PADDI to R10C13D.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to StrobeGenerator_inst/SLICE_11: Name Fanout Delay (ns) Site Resource ROUTE 97 2.001 20.PADDI to R10C11B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 32.113ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q StrobeGenerator_inst/Counter_i21 (from Clock_c +) Destination: FF Data in StrobeGenerator_inst/Counter_i0 (to Clock_c +) Delay: 7.639ns (23.1% logic, 76.9% route), 4 logic levels. Constraint Details: 7.639ns physical path delay StrobeGenerator_inst/SLICE_1 to StrobeGenerator_inst/SLICE_12 meets 40.000ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 39.752ns) by 32.113ns Physical Path Details: Data path StrobeGenerator_inst/SLICE_1 to StrobeGenerator_inst/SLICE_12: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R10C13D.CLK to R10C13D.Q0 StrobeGenerator_inst/SLICE_1 (from Clock_c) ROUTE 2 1.331 R10C13D.Q0 to R7C14A.A0 StrobeGenerator_inst/Counter_21 CTOF_DEL --- 0.452 R7C14A.A0 to R7C14A.F0 SLICE_97 ROUTE 1 1.057 R7C14A.F0 to R10C14C.C1 StrobeGenerator_inst/n32 CTOF_DEL --- 0.452 R10C14C.C1 to R10C14C.F1 SLICE_108 ROUTE 1 1.324 R10C14C.F1 to R7C12C.A0 StrobeGenerator_inst/n46 CTOF_DEL --- 0.452 R7C12C.A0 to R7C12C.F0 StrobeGenerator_inst/SLICE_93 ROUTE 16 2.162 R7C12C.F0 to R10C11A.LSR StrobeGenerator_inst/Strobe_o_N_116 (to Clock_c) -------- 7.639 (23.1% logic, 76.9% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to StrobeGenerator_inst/SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 97 2.001 20.PADDI to R10C13D.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to StrobeGenerator_inst/SLICE_12: Name Fanout Delay (ns) Site Resource ROUTE 97 2.001 20.PADDI to R10C11A.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 32.113ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q StrobeGenerator_inst/Counter_i21 (from Clock_c +) Destination: FF Data in StrobeGenerator_inst/Counter_i18 (to Clock_c +) FF StrobeGenerator_inst/Counter_i17 Delay: 7.639ns (23.1% logic, 76.9% route), 4 logic levels. Constraint Details: 7.639ns physical path delay StrobeGenerator_inst/SLICE_1 to StrobeGenerator_inst/SLICE_3 meets 40.000ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 39.752ns) by 32.113ns Physical Path Details: Data path StrobeGenerator_inst/SLICE_1 to StrobeGenerator_inst/SLICE_3: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R10C13D.CLK to R10C13D.Q0 StrobeGenerator_inst/SLICE_1 (from Clock_c) ROUTE 2 1.331 R10C13D.Q0 to R7C14A.A0 StrobeGenerator_inst/Counter_21 CTOF_DEL --- 0.452 R7C14A.A0 to R7C14A.F0 SLICE_97 ROUTE 1 1.057 R7C14A.F0 to R10C14C.C1 StrobeGenerator_inst/n32 CTOF_DEL --- 0.452 R10C14C.C1 to R10C14C.F1 SLICE_108 ROUTE 1 1.324 R10C14C.F1 to R7C12C.A0 StrobeGenerator_inst/n46 CTOF_DEL --- 0.452 R7C12C.A0 to R7C12C.F0 StrobeGenerator_inst/SLICE_93 ROUTE 16 2.162 R7C12C.F0 to R10C13B.LSR StrobeGenerator_inst/Strobe_o_N_116 (to Clock_c) -------- 7.639 (23.1% logic, 76.9% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to StrobeGenerator_inst/SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 97 2.001 20.PADDI to R10C13D.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to StrobeGenerator_inst/SLICE_3: Name Fanout Delay (ns) Site Resource ROUTE 97 2.001 20.PADDI to R10C13B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 32.113ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q StrobeGenerator_inst/Counter_i21 (from Clock_c +) Destination: FF Data in StrobeGenerator_inst/Counter_i22 (to Clock_c +) FF StrobeGenerator_inst/Counter_i21 Delay: 7.639ns (23.1% logic, 76.9% route), 4 logic levels. Constraint Details: 7.639ns physical path delay StrobeGenerator_inst/SLICE_1 to StrobeGenerator_inst/SLICE_1 meets 40.000ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 39.752ns) by 32.113ns Physical Path Details: Data path StrobeGenerator_inst/SLICE_1 to StrobeGenerator_inst/SLICE_1: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R10C13D.CLK to R10C13D.Q0 StrobeGenerator_inst/SLICE_1 (from Clock_c) ROUTE 2 1.331 R10C13D.Q0 to R7C14A.A0 StrobeGenerator_inst/Counter_21 CTOF_DEL --- 0.452 R7C14A.A0 to R7C14A.F0 SLICE_97 ROUTE 1 1.057 R7C14A.F0 to R10C14C.C1 StrobeGenerator_inst/n32 CTOF_DEL --- 0.452 R10C14C.C1 to R10C14C.F1 SLICE_108 ROUTE 1 1.324 R10C14C.F1 to R7C12C.A0 StrobeGenerator_inst/n46 CTOF_DEL --- 0.452 R7C12C.A0 to R7C12C.F0 StrobeGenerator_inst/SLICE_93 ROUTE 16 2.162 R7C12C.F0 to R10C13D.LSR StrobeGenerator_inst/Strobe_o_N_116 (to Clock_c) -------- 7.639 (23.1% logic, 76.9% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to StrobeGenerator_inst/SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 97 2.001 20.PADDI to R10C13D.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to StrobeGenerator_inst/SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 97 2.001 20.PADDI to R10C13D.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 32.113ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q StrobeGenerator_inst/Counter_i21 (from Clock_c +) Destination: FF Data in StrobeGenerator_inst/Counter_i14 (to Clock_c +) FF StrobeGenerator_inst/Counter_i13 Delay: 7.639ns (23.1% logic, 76.9% route), 4 logic levels. Constraint Details: 7.639ns physical path delay StrobeGenerator_inst/SLICE_1 to StrobeGenerator_inst/SLICE_5 meets 40.000ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 39.752ns) by 32.113ns Physical Path Details: Data path StrobeGenerator_inst/SLICE_1 to StrobeGenerator_inst/SLICE_5: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R10C13D.CLK to R10C13D.Q0 StrobeGenerator_inst/SLICE_1 (from Clock_c) ROUTE 2 1.331 R10C13D.Q0 to R7C14A.A0 StrobeGenerator_inst/Counter_21 CTOF_DEL --- 0.452 R7C14A.A0 to R7C14A.F0 SLICE_97 ROUTE 1 1.057 R7C14A.F0 to R10C14C.C1 StrobeGenerator_inst/n32 CTOF_DEL --- 0.452 R10C14C.C1 to R10C14C.F1 SLICE_108 ROUTE 1 1.324 R10C14C.F1 to R7C12C.A0 StrobeGenerator_inst/n46 CTOF_DEL --- 0.452 R7C12C.A0 to R7C12C.F0 StrobeGenerator_inst/SLICE_93 ROUTE 16 2.162 R7C12C.F0 to R10C12D.LSR StrobeGenerator_inst/Strobe_o_N_116 (to Clock_c) -------- 7.639 (23.1% logic, 76.9% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to StrobeGenerator_inst/SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 97 2.001 20.PADDI to R10C13D.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to StrobeGenerator_inst/SLICE_5: Name Fanout Delay (ns) Site Resource ROUTE 97 2.001 20.PADDI to R10C12D.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 32.113ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q StrobeGenerator_inst/Counter_i21 (from Clock_c +) Destination: FF Data in StrobeGenerator_inst/Counter_i10 (to Clock_c +) FF StrobeGenerator_inst/Counter_i9 Delay: 7.639ns (23.1% logic, 76.9% route), 4 logic levels. Constraint Details: 7.639ns physical path delay StrobeGenerator_inst/SLICE_1 to StrobeGenerator_inst/SLICE_7 meets 40.000ns delay constraint less 0.000ns skew and 0.248ns LSR_SET requirement (totaling 39.752ns) by 32.113ns Physical Path Details: Data path StrobeGenerator_inst/SLICE_1 to StrobeGenerator_inst/SLICE_7: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 R10C13D.CLK to R10C13D.Q0 StrobeGenerator_inst/SLICE_1 (from Clock_c) ROUTE 2 1.331 R10C13D.Q0 to R7C14A.A0 StrobeGenerator_inst/Counter_21 CTOF_DEL --- 0.452 R7C14A.A0 to R7C14A.F0 SLICE_97 ROUTE 1 1.057 R7C14A.F0 to R10C14C.C1 StrobeGenerator_inst/n32 CTOF_DEL --- 0.452 R10C14C.C1 to R10C14C.F1 SLICE_108 ROUTE 1 1.324 R10C14C.F1 to R7C12C.A0 StrobeGenerator_inst/n46 CTOF_DEL --- 0.452 R7C12C.A0 to R7C12C.F0 StrobeGenerator_inst/SLICE_93 ROUTE 16 2.162 R7C12C.F0 to R10C12B.LSR StrobeGenerator_inst/Strobe_o_N_116 (to Clock_c) -------- 7.639 (23.1% logic, 76.9% route), 4 logic levels. Clock Skew Details: Source Clock Path Clock to StrobeGenerator_inst/SLICE_1: Name Fanout Delay (ns) Site Resource ROUTE 97 2.001 20.PADDI to R10C13D.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to StrobeGenerator_inst/SLICE_7: Name Fanout Delay (ns) Site Resource ROUTE 97 2.001 20.PADDI to R10C12B.CLK Clock_c -------- 2.001 (0.0% logic, 100.0% route), 0 logic levels. Report: 126.791MHz is the maximum frequency for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "Clock_c" 25.000000 MHz ; | 25.000 MHz| 126.791 MHz| 4 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: Clock_c Source: Clock.PAD Loads: 97 Covered under: FREQUENCY NET "Clock_c" 25.000000 MHz ; Timing summary (Setup): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 2010 paths, 1 nets, and 893 connections (81.78% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.13.0.56.2 Thu Feb 08 21:41:58 2024 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2023 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 10 -gt -sethld -sp 5 -sphld m -o Kurs24_impl1.twr -gui Kurs24_impl1.ncd Kurs24_impl1.prf Design file: kurs24_impl1.ncd Preference file: kurs24_impl1.prf Device,speed: LCMXO2-1200HC,m Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- Preference Summary
  • FREQUENCY NET "Clock_c" 25.000000 MHz (0 errors)
  • 2010 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "Clock_c" 25.000000 MHz ; 2010 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.306ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q Synchronizer_inst/R2_0__9 (from Clock_c +) Destination: FF Data in EdgeDetector_inst/Previous_13 (to Clock_c +) Delay: 0.287ns (46.3% logic, 53.7% route), 1 logic levels. Constraint Details: 0.287ns physical path delay SLICE_95 to SLICE_95 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.306ns Physical Path Details: Data path SLICE_95 to SLICE_95: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C16D.CLK to R7C16D.Q0 SLICE_95 (from Clock_c) ROUTE 2 0.154 R7C16D.Q0 to R7C16D.M1 SignalSync (to Clock_c) -------- 0.287 (46.3% logic, 53.7% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to SLICE_95: Name Fanout Delay (ns) Site Resource ROUTE 97 0.773 20.PADDI to R7C16D.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to SLICE_95: Name Fanout Delay (ns) Site Resource ROUTE 97 0.773 20.PADDI to R7C16D.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.308ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DoubleDabble_inst/BCD__i20 (from Clock_c +) Destination: FF Data in DoubleDabble_inst/BCD_o_i0_i20 (to Clock_c +) Delay: 0.289ns (46.0% logic, 54.0% route), 1 logic levels. Constraint Details: 0.289ns physical path delay DoubleDabble_inst/SLICE_66 to DoubleDabble_inst/SLICE_124 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.308ns Physical Path Details: Data path DoubleDabble_inst/SLICE_66 to DoubleDabble_inst/SLICE_124: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C16A.CLK to R8C16A.Q1 DoubleDabble_inst/SLICE_66 (from Clock_c) ROUTE 6 0.156 R8C16A.Q1 to R8C16B.M1 DoubleDabble_inst/BCD_20 (to Clock_c) -------- 0.289 (46.0% logic, 54.0% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to DoubleDabble_inst/SLICE_66: Name Fanout Delay (ns) Site Resource ROUTE 97 0.773 20.PADDI to R8C16A.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DoubleDabble_inst/SLICE_124: Name Fanout Delay (ns) Site Resource ROUTE 97 0.773 20.PADDI to R8C16B.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.308ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DoubleDabble_inst/BCD__i28 (from Clock_c +) Destination: FF Data in DoubleDabble_inst/BCD_o_i0_i28 (to Clock_c +) Delay: 0.289ns (46.0% logic, 54.0% route), 1 logic levels. Constraint Details: 0.289ns physical path delay DoubleDabble_inst/SLICE_70 to SLICE_132 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.308ns Physical Path Details: Data path DoubleDabble_inst/SLICE_70 to SLICE_132: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C12D.CLK to R7C12D.Q1 DoubleDabble_inst/SLICE_70 (from Clock_c) ROUTE 6 0.156 R7C12D.Q1 to R7C12A.M1 DoubleDabble_inst/BCD_28 (to Clock_c) -------- 0.289 (46.0% logic, 54.0% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to DoubleDabble_inst/SLICE_70: Name Fanout Delay (ns) Site Resource ROUTE 97 0.773 20.PADDI to R7C12D.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to SLICE_132: Name Fanout Delay (ns) Site Resource ROUTE 97 0.773 20.PADDI to R7C12A.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.309ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DoubleDabble_inst/BCD__i7 (from Clock_c +) Destination: FF Data in DoubleDabble_inst/BCD_o_i0_i7 (to Clock_c +) Delay: 0.290ns (45.9% logic, 54.1% route), 1 logic levels. Constraint Details: 0.290ns physical path delay DoubleDabble_inst/SLICE_60 to SLICE_116 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.309ns Physical Path Details: Data path DoubleDabble_inst/SLICE_60 to SLICE_116: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R9C15A.CLK to R9C15A.Q0 DoubleDabble_inst/SLICE_60 (from Clock_c) ROUTE 5 0.157 R9C15A.Q0 to R9C13A.M1 DoubleDabble_inst/BCD_7 (to Clock_c) -------- 0.290 (45.9% logic, 54.1% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to DoubleDabble_inst/SLICE_60: Name Fanout Delay (ns) Site Resource ROUTE 97 0.773 20.PADDI to R9C15A.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to SLICE_116: Name Fanout Delay (ns) Site Resource ROUTE 97 0.773 20.PADDI to R9C13A.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.310ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DoubleDabble_inst/BCD__i21 (from Clock_c +) Destination: FF Data in DoubleDabble_inst/BCD_o_i0_i21 (to Clock_c +) Delay: 0.291ns (45.7% logic, 54.3% route), 1 logic levels. Constraint Details: 0.291ns physical path delay DoubleDabble_inst/SLICE_67 to DoubleDabble_inst/SLICE_122 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.310ns Physical Path Details: Data path DoubleDabble_inst/SLICE_67 to DoubleDabble_inst/SLICE_122: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C16D.CLK to R8C16D.Q0 DoubleDabble_inst/SLICE_67 (from Clock_c) ROUTE 6 0.158 R8C16D.Q0 to R8C15D.M0 DoubleDabble_inst/BCD_21 (to Clock_c) -------- 0.291 (45.7% logic, 54.3% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to DoubleDabble_inst/SLICE_67: Name Fanout Delay (ns) Site Resource ROUTE 97 0.773 20.PADDI to R8C16D.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DoubleDabble_inst/SLICE_122: Name Fanout Delay (ns) Site Resource ROUTE 97 0.773 20.PADDI to R8C15D.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.312ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DoubleDabble_inst/BCD__i14 (from Clock_c +) Destination: FF Data in DoubleDabble_inst/BCD_o_i0_i14 (to Clock_c +) Delay: 0.293ns (45.4% logic, 54.6% route), 1 logic levels. Constraint Details: 0.293ns physical path delay DoubleDabble_inst/SLICE_63 to DoubleDabble_inst/SLICE_123 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.312ns Physical Path Details: Data path DoubleDabble_inst/SLICE_63 to DoubleDabble_inst/SLICE_123: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C15A.CLK to R8C15A.Q1 DoubleDabble_inst/SLICE_63 (from Clock_c) ROUTE 5 0.160 R8C15A.Q1 to R8C15B.M0 DoubleDabble_inst/BCD_14 (to Clock_c) -------- 0.293 (45.4% logic, 54.6% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to DoubleDabble_inst/SLICE_63: Name Fanout Delay (ns) Site Resource ROUTE 97 0.773 20.PADDI to R8C15A.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DoubleDabble_inst/SLICE_123: Name Fanout Delay (ns) Site Resource ROUTE 97 0.773 20.PADDI to R8C15B.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.312ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DoubleDabble_inst/BCD__i11 (from Clock_c +) Destination: FF Data in DoubleDabble_inst/BCD_o_i0_i11 (to Clock_c +) Delay: 0.293ns (45.4% logic, 54.6% route), 1 logic levels. Constraint Details: 0.293ns physical path delay DoubleDabble_inst/SLICE_62 to DoubleDabble_inst/SLICE_107 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.312ns Physical Path Details: Data path DoubleDabble_inst/SLICE_62 to DoubleDabble_inst/SLICE_107: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R7C15C.CLK to R7C15C.Q0 DoubleDabble_inst/SLICE_62 (from Clock_c) ROUTE 5 0.160 R7C15C.Q0 to R7C13C.M1 DoubleDabble_inst/BCD_11 (to Clock_c) -------- 0.293 (45.4% logic, 54.6% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to DoubleDabble_inst/SLICE_62: Name Fanout Delay (ns) Site Resource ROUTE 97 0.773 20.PADDI to R7C15C.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DoubleDabble_inst/SLICE_107: Name Fanout Delay (ns) Site Resource ROUTE 97 0.773 20.PADDI to R7C13C.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.321ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DoubleDabble_inst/BCD__i1 (from Clock_c +) Destination: FF Data in DoubleDabble_inst/BCD_o_i0_i1 (to Clock_c +) Delay: 0.302ns (44.0% logic, 56.0% route), 1 logic levels. Constraint Details: 0.302ns physical path delay DoubleDabble_inst/SLICE_57 to DoubleDabble_inst/SLICE_131 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.321ns Physical Path Details: Data path DoubleDabble_inst/SLICE_57 to DoubleDabble_inst/SLICE_131: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R9C16B.CLK to R9C16B.Q0 DoubleDabble_inst/SLICE_57 (from Clock_c) ROUTE 6 0.169 R9C16B.Q0 to R9C16D.M1 DoubleDabble_inst/BCD_1 (to Clock_c) -------- 0.302 (44.0% logic, 56.0% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to DoubleDabble_inst/SLICE_57: Name Fanout Delay (ns) Site Resource ROUTE 97 0.773 20.PADDI to R9C16B.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DoubleDabble_inst/SLICE_131: Name Fanout Delay (ns) Site Resource ROUTE 97 0.773 20.PADDI to R9C16D.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.322ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DoubleDabble_inst/BCD__i15 (from Clock_c +) Destination: FF Data in DoubleDabble_inst/BCD_o_i0_i15 (to Clock_c +) Delay: 0.303ns (43.9% logic, 56.1% route), 1 logic levels. Constraint Details: 0.303ns physical path delay DoubleDabble_inst/SLICE_64 to DoubleDabble_inst/SLICE_123 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.322ns Physical Path Details: Data path DoubleDabble_inst/SLICE_64 to DoubleDabble_inst/SLICE_123: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R8C15C.CLK to R8C15C.Q0 DoubleDabble_inst/SLICE_64 (from Clock_c) ROUTE 5 0.170 R8C15C.Q0 to R8C15B.M1 DoubleDabble_inst/BCD_15 (to Clock_c) -------- 0.303 (43.9% logic, 56.1% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to DoubleDabble_inst/SLICE_64: Name Fanout Delay (ns) Site Resource ROUTE 97 0.773 20.PADDI to R8C15C.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DoubleDabble_inst/SLICE_123: Name Fanout Delay (ns) Site Resource ROUTE 97 0.773 20.PADDI to R8C15B.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Passed: The following path meets requirements by 0.324ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q DoubleDabble_inst/BCD__i0 (from Clock_c +) Destination: FF Data in DoubleDabble_inst/BCD_o_i0_i0 (to Clock_c +) Delay: 0.305ns (43.6% logic, 56.4% route), 1 logic levels. Constraint Details: 0.305ns physical path delay DoubleDabble_inst/SLICE_56 to DoubleDabble_inst/SLICE_131 meets -0.019ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.019ns) by 0.324ns Physical Path Details: Data path DoubleDabble_inst/SLICE_56 to DoubleDabble_inst/SLICE_131: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.133 R9C16A.CLK to R9C16A.Q0 DoubleDabble_inst/SLICE_56 (from Clock_c) ROUTE 6 0.172 R9C16A.Q0 to R9C16D.M0 DoubleDabble_inst/BCD_0 (to Clock_c) -------- 0.305 (43.6% logic, 56.4% route), 1 logic levels. Clock Skew Details: Source Clock Path Clock to DoubleDabble_inst/SLICE_56: Name Fanout Delay (ns) Site Resource ROUTE 97 0.773 20.PADDI to R9C16A.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Destination Clock Path Clock to DoubleDabble_inst/SLICE_131: Name Fanout Delay (ns) Site Resource ROUTE 97 0.773 20.PADDI to R9C16D.CLK Clock_c -------- 0.773 (0.0% logic, 100.0% route), 0 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "Clock_c" 25.000000 MHz ; | 0.000 ns| 0.306 ns| 1 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: Clock_c Source: Clock.PAD Loads: 97 Covered under: FREQUENCY NET "Clock_c" 25.000000 MHz ; Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 2010 paths, 1 nets, and 893 connections (81.78% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 0 (setup), 0 (hold) Score: 0 (setup), 0 (hold) Cumulative negative slack: 0 (0+0) -------------------------------------------------------------------------------- --------------------------------------------------------------------------------